1. Field of the Invention
The present invention pertains to semiconductor structures and fabrication techniques. More particularly, the present invention pertains to the integration of bipolar technology structures into CMOS circuits utilizing CMOS processing technology. The present invention is a bipolar lateral pass-transistor for use in CMOS integrated circuit ("IC") applications and a process for fabricating it. The bipolar transistor structure of the present invention has a high immunity to latch-up and has improved high frequency characteristics.
2. The Prior Art
Junction isolated CMOS technologies are increasingly being used for analog and analog/digital integrated circuits. One of the limitations to date has been the implementation of a low on-resistance switch for sourcing high currents from a positive supply. A low on-resistance MOS P-channel transistor, for example, occupies a large silicon area compared to a conventional bipolar PNP transistor. The difference in silicon area can be up to ten times larger depending on a variety of considerations, including gate drive voltage, gate oxide thickness etc., resulting in higher manufacturing costs and less efficient use of silicon chip area.
There is a group of common circuit functions such as low dropout linear voltage regulators/battery backup circuits, which require one low on-resistance switch coupled with a multiplicity of additional circuitry, such as error amplifiers, voltage references and logic. The use of bipolar transistor technology for configuring such low on-resistance switches has decided advantages, not the least of which is the reduction of silicon area. The integration of such bipolar technology with MOS technology, however, raises several well-known problems. The most well-known of these problems is the familiar latch-up which occurs when the PN junctions inherent in such a structure become forward biased.
One bipolar transistor for use in MOS technologies would be of the lateral type wherein the collector and emitter are P-type diffusions in an N-type substrate which is used as the base. This type of PNP transistor is commonly called a lateral PNP transistor due to the fact that the average collector to emitter current flows in a lateral direction parallel to the surface of the silicon.
It has been customary to avoid this bipolar structure in CMOS circuit structures because of the inherent latch-up problem and the limitation on its usefulness because its base is at the same potential a the substrate of the integrated circuit. If the emitter of such a PNP transistor is connected to the positive supply of the IC, collector current will be undefined and virtually uncontrolled, and minority carriers, injected into the base, will be collected by the collector and the other P regions comprising the drain and source of P channel transistors and the P-wells or substrate of the N channel transistors for a P-well CMOS technology. If a sufficient amount of this injected current is collected by the P-well devices then the well-known phenomena of latch-up may occur.
As the use of CMOS circuitry increases, the number and variations of circuits will also increase. Because of considerations, such as size, already mentioned, it would be useful to incorporate such a lateral PNP transistor into existing CMOS designs. Therefore, there is a need for a structure and technique for creating a lateral PNP transistor having as its base region the substrate of the integrated circuit, which avoids the latch-up and other problems encountered by currently-known technology.
Another problem which is encountered when trying to integrate a lateral PNP transistor into a CMOS structure relates to the frequency characteristics of the device. Because of the random paths that minority carriers generated by the base may take, the mean lifetime of the minority carriers is relatively long. This phenomenon degrades high frequency characteristics of the device.